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Logic Synthesis and Verification Algorithms

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Paru le : 1996

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.Logic Synthesis ...
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Description du livre


Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

À propos

Auteur
A. N. Netravali , F. Somenzi , G.D. Hachtel
Éditeur
Kluwer Academic Publishers
Collection
n.c
Parution
1996
Pages
n.c
EAN papier
0306475928

Caractéristiques détaillées - droits

EAN PDF
0306475928
Prix
156,49 €
Nombre pages copiables
1
Nombre pages imprimables
10
Taille du fichier
1445 Ko
Ce livre est accessible aux handicaps informations d'accessibilité

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